1. Field of the Invention
The present invention relates to a programmable buffer circuit for receiving a control signal, which is preferable for application to a semiconductor device such as a semiconductor memory or the like, and more particularly to a programmable buffer circuit enabling high density integration and a mask ROM device having the same.
2. Description of the Related Art
Generally, various kinds of plural signal pins are provided on a semiconductor device such as a microprocessor, a dynamic random access memory (DRAM), a mask ROM and the like to output a signal out of the same devices and input a signal from outside thereof. A control signal pin for receiving a control signal is enumerated as the signal pin as well as a pin for data input/output and a pin for address input/output. Selecting whether a semiconductor device provided with such a control signal pin is in activated state or non-activated state, selecting an operation of the semiconductor device and the like are carried out by a control signal supplied to the control signal pins. For example, the above-mentioned mask ROM usually contains a chip-enable terminal (CE terminal). Whether the chip is to be activated or not activated can be controlled according to a chip-enable signal (CE signal) supplied to a CE terminal from outside of the chip. That is, when the chip is of low active type, if the CE signal is low level, the chip is activated. If the signal is high level, the chip is in not activated state. Further, when the chip is of high active type, if the CE signal is high level, the chip is activated and if the signal is low level, the chip is in not activated state.
However, whether the chip is of low active type or high active type is usually selected according to user's request. If a manufacturer intends to produce both a low active type product and a high active type product to meet such a customer's request, the product line is diversified. As a result, the production cost increases. Therefore, this countermeasure is not preferable in economic viewpoints.
From this viewpoint, such a technology which enables adaptation of a chip to both low active type and high active type by providing a programmable buffer circuit inside the chip and introducing a program into the circuit has been proposed (Japanese Unexamined Patent Publication No. Sho 61-9017).
FIG. 1 is a circuit diagram showing a conventional programmable buffer circuit. An external CE terminal 50 to which a CE signal is to be supplied from outside and an internal CE terminal 51 to be connected to an internal circuit such as a memory cell array, a control circuit or the like are provided in a conventional programmable buffer circuit. Further, a NOR circuit 52 and an exclusive OR circuit 53 are connected in series from the external CE terminal 50 in this order between the external CE terminal 50 and the internal CE terminal 51.
The external CE terminal 50 is connected to one input terminal of the NOR circuit 52 and a selective signal generating circuit 54 is connected to the other input terminal of the NOR circuit 52. Further, the output terminal of the NOR circuit 52 is connected to one input terminal of the exclusive OR circuit 53 and the selective signal generating circuit 55 is connected to the other input terminal of the exclusive OR circuit 53.
In each of the selective signal generating circuits 54 and 55, two switches are connected in series between a power supply and ground. One input terminal of the NOR circuit 52 and one input terminal of the exclusive OR circuit 53 are each connected to a connection point between these switches. The logical level of the selective signal which is transmitted from the selective signal generating circuits 54 or 55 to the input terminal of the NOR circuit 52 or the exclusive OR circuit 53 is determined by the switches provided in the selective signal generating circuits 54 or 55. Because the logical level thereof is selected by user, conduction or non-conduction of the switch is determined by selection of the user.
Next, an operation of the conventional programmable buffer circuit having such a structure will be described.
Assume that a low active type semiconductor memory is used as an internal circuit connected to the internal CE terminal 51. That is, when the internal CE terminal 51 is set in low level, the semiconductor memory is activated.
When the semiconductor memory is of low active type, if the user's request is low active type, only the grounding side switch of the selective signal generating circuit 54 is made conductive, and only the power supply side switch of the selective signal generating circuit 55 is made conductive. As a result, a selective signal transmitted from the selective signal generating circuit 54 becomes of low level and a selective signal transmitted from the selective signal generating circuit 55 becomes of high level. Then, the logical level of a signal to be transmitted to the internal CE terminal 51 becomes of the same phase as a signal supplied to the external CE terminal 50. Thus, the programmable buffer circuit becomes low active type, so that the user's request is satisfied.
On the other hand, if the user's request is high active type, only the grounding side switches of the selective signal generating circuits 54 and 55 are made conductive. As a result, both selective signals transmitted from the selective signal generating circuits 54 and 55 become of low level. The logical level of a signal transmitted to the internal CE terminal 51 becomes of the opposite phase to a signal supplied to the external CE terminal 50. Thus, the programmable buffer circuit becomes high active type, so that the user's request is satisfied.
If the user's request is "don't care" type or a type of active irrespective of the logical level of a signal supplied to the external CE terminal 50, only the power supply side switch of the selective signal generating circuit 54 is made conductive, while only the grounding side switch of the selective signal generating circuit 55 is made conductive. As a result, a selective signal transmitted from the selective signal generating circuit 54 becomes of high level and a selective signal transmitted from the selective signal generating circuit 55 becomes of low level. Then, the logical level of a signal transmitted to the internal CE terminal 51 is low level irrespective of a signal supplied to the external CE terminal 50. Thus, the programmable buffer circuit becomes "don't care" type, so that the user's request is satisfied.
However, the above-mentioned conventional programmable buffer circuit requires relatively many devices and most chip area is occupied by the programmable buffer circuit.
That is, the programmable buffer circuit shown in FIG. 1 requires the NOR circuit 52 and the exclusive OR circuit 53, and the NOR circuit 52 and the exclusive OR circuit 53 are constituted of many devices. FIG. 2 is a circuit diagram indicating a NOR circuit on transistor level, and FIG. 3 is a circuit diagram indicating an exclusive OR circuit on transistor level. As shown in FIG. 2, a NOR circuit is constituted of four transistors on transistor level. Further, as shown in FIG. 3, an exclusive OR circuit is constituted of 14 transistors on transistor level.
Therefore, as shown in FIGS. 1-3, totally 18 transistors are needed in the conventional programmable buffer circuit. Further, the switch elements for constituting the selective signal generating circuits 54 and 55 are also needed. Thus, an area on which these components are formed is relatively large.